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The components are interconnected with corresponding signal values. We are almost done with the last segment of the code. The intermediary values T1, T2, T3 are declared first. ![]() The next task is to interconnect the two half adders and the OR gate. The half adder code is given above and for VHDL OR gate code, you can refer using the link. Note: Before scripting the VHDL code for Full adder, make sure to successfully compile the sub-components half adder and OR gate. So here, “component half_adder” and “component or_gate” are the sub-components. In general, the subcomponents are defined by “component label”. Here, the sub-components that are used are half-adder and OR gate. Next, the architecture is defined and the sub-components are defined. First, the libraries are imported as usual and the entity is declared with the label “full_adder” and the Inputs A, B, and Outputs sum, carry_out are declared. Let's break the above code for better understanding. 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